Strained-silicon technology is a promising route to enhance metal-oxide-semiconductor field-effect transistor (MOSFET) performance due to improved carrier transport properties.
In particular, biaxially-strained silicon on insulator substrate (abbreviated SSOI) is a promising source of strain engineering for the future CMOS technology nodes. The tensile stress in the Si layer results in an increased carrier mobility with respect to unstrained SOI. This in turn results in an enhanced drive current.
As the scaling of strained-Si MOSFETs continues, the performance enhancement may become susceptible to degradation during processing, particularly from ion implantation and thermal processing effects.
More specifically, the ion implant dose under the gate (e.g., associated with the halo and/or extensions implants) increases with scaling. In addition, the damage associated with the source/drain extension regions may comprise a larger portion of the channel as the device is scaled. Ion implantation damage may supply point defects that assist the relaxation of strain or the up-diffusion of species (e.g. Ge) from the underlying layers.
Moreover, residual ion implantation damage remaining after thermal annealing may act as carrier scattering centers. In strained-Si films thermal processing such as i.e. post implantation anneal can cause misfit dislocations, leading to strain relaxation as well as enhanced impurity diffusion, resulting ultimately in decreased carrier mobility.
When compared to planar junctions, junction formation on multi-gate 3-D structures, commonly referred to as FinFET or MuGFET present additional challenges in achieving conformal doping profiles. More specifically, because of the unidirectional nature of the ion beam and of the shadowing effect at elevated structures (fins), it becomes more and more difficult to achieve a conformal FinFET junction using conventional ion implantation technique.
In addition to that, for very narrow fin structures the amorphization caused by the conventional ion implantation cannot be fully recovered by thermal anneal.
Despite the progress in the art, there is still need for a method for doping strained semiconductor layers or narrow semiconductor structures (e.g. fin structures in FinFET devices) that can replace the conventional ion implantation technique and possibly the subsequent thermal annealing steps, while keeping the device performance un-altered or improving it.